Virtual Design of an Audio Life logging System by Mark Erby

Author:Mark Erby [Erby, Mark]
Language: eng
Format: azw3
Published: 2018-10-21T16:00:00+00:00

All digital systems generally use a clock signal for synchronization, and cycle-accurate mod-els are written to simulate each module in the systems for just 1 clock cycle of operation, then repeat again for each module in the next clock cycle. However, a problem with switching from one module to another every clock cycle is very slow simulation speed. It is better to simulate as many clock cycles of activity as possible before switching, as each simulator context switch is expensive in terms of the time needed to save and restore the model state. Architecture and higher level models written in SystemC avoid context switching every clock cycle. ey do this in SystemC by using two methods to avoid context switches, event processing and temporal decoupling.

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